Hello
I am designing a power-critical coin cell device employing an MPU-9250 and microcontroller. I require the device to operate down to a cell voltage of 2V so have a small boost converter to drive the MPU-9250 (since min. operating voltage 2.4V). The microcontroller is powered direct from coin cell such that boost converter and MPU-9250 can be turned off to save power. Coin cell provides between 2.0 and 3.0V. Boost converter outputs 3.0V (or load disconnect when off).
MPU-9250 datasheet §4.23 makes three points:
1. During power up and in normal operation VDDIO must not exceed VDD.
2. During power up, VDD and VDDIO must be monotonic ramps.
3. Table 4 states VDD rise time must fall between 0.1ms and 100ms.
I would like VDDIO to be supplied from the same microcontroller IO pin that enables the boost converter. This means VDDIO will follow battery voltage from 3.0 to 2.0V as it goes flat, while VDD remains at 3.0V, so steady state VDDIO is always less than VDD. Unfortunately with IO line driving VDDIO, VDDIO will be present before VDD due to boost converter start up time. As such I have proposed RC delay on VDDIO such that it remains lower than VDD on start-up and to meet monotonic ramp requirement. I presume by doing the this that all requirements are met, but this feels risky and unorthodox.
How critical is the monotonic ramp requirement for VDDIO? Could I simply use separate IO pin to enable VDDIO after VDD has stabilised (set boost enable high, wait, set VDDIO high)? Bare in mind this would then mean for a short period VDDIO is less than the minimum 1.71V required, so what impact would this have?
I notice in “InvenSense-Motion-Sensor-Universal-EV-User-Guide3” Universal EVB schematic if VDD is selected as 3V0 (from linear regulator) and VDDIO is selected as 1V8 from CN1 header, then there is no guarantee that requirement 1 and 2 are met, so am I overthinking this in my own circuit? Are there other examples of VDDIO/VDD setups?