SmartIndustrial™ Industrial MEMS Motion Sensors

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By jbianchettitra… , 11 April 2025

Hi. We have a IIM-42352 sensor configured for 16KHz of ODR, ±16g of Full-Scale range, FIFO mode and INTF_CONFIG0.FIFO_HOLD_LAST_DATA_EN register bit set to 1.

We are observing that when the sensor is submitted to an amplitude greater than 16g, sometimes the output goes down to -32768 (as shown in the attachments). We couldn't find any information in the datasheet about the behavior on these conditions, if it's normal or the value should be clipped at the positive value.

By deanharkenuavi… , 10 January 2025

The datasheet (DS-000300) indicates both UART commands as well as SPI accessible registers. It appears that the UART interface could be ignored and only the SPI interface could be used. If that is true, then I want to use SPI only.

My problem with understanding how to a SPI only interface is how do I use the "page ID"? All the data registers are on page 1. I only have 8 bits of SPI register address to work with and page 0 is full.

By southernbamboo… , 7 December 2024

Hello,

The EV_IIM-42652 Evaluation Board has a user guide at https://invensense.tdk.com/download-pdf/an-000491-tdk-invensense-ev_iim-42652-evaluation-board-evb-user-guide/

The schematic in that docuement shows that pin 19 on connector is named "5V_AP". I'm wondering what voltage range is suitable for that input. Does anyone know?

Specifically, if I have 3.3V easily accessible to me - can I provide just 3.3V to pin 19 to save myself from jumping through some hoops, or is it necessary to provide something that's much closer to 5V?

By mxmtargmailcom , 28 November 2024

Hi team,

Could you give me some additional ideas how to engage ODR clock routing to PIN12 if any?
I use for an evaluation DK20670 with dedicated software.
I try to execute
int inv_iim20670_routeODRclock_to_pin12(struct inv_iim20670 *s)
function but it failed with INV_ERROR_TRANSPORT.
It happens on reading BANK3 register 0x16. Protocol returns RS1=1 RS0=0.
Moreover, after that the chip communicates improperly and becomes operational after power-off/power-on cycle.

The same behavior occurs after an attempt to exec inv_iim20670_set_register_write_lock()